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d a t a sh eet preliminary speci?cation file under integrated circuits, ic01 1997 mar 13 integrated circuits TEA6324t sound control circuit
1997 mar 13 2 philips semiconductors preliminary speci?cation sound control circuit TEA6324t features source selector for two stereo and one mono inputs interface for noise reduction circuits interface for external equalizer volume and balance control bass control with equalizer filters treble control mute control at audio signal zero crossing fast mute control via i 2 c-bus fast mute control via pin i 2 c-bus control for all functions power supply with internal power-on reset. general description the sound control circuit TEA6324t is an i 2 c-bus controlled stereo preamplifier for car radio hi-fi sound applications. quick reference data ordering information symbol parameter conditions min. typ. max. unit v cc supply voltage 7.5 8.5 9.5 v i cc supply current v cc = 8.5 v - 26 - ma v o(rms) maximum output voltage level v cc = 8.5 v; thd 0.1% - 2000 - mv g v voltage gain - 86 - +20 db g step(vol) step resolution (volume) - 1 - db g bass bass control - 18 - +18 db g treble treble control - 12 - +12 db g step(treble) step resolution (treble) - 1.5 - db (s+n)/n signal-plus-noise to noise ratio v o = 2.0 v; g v = 0 db; unweighted - 105 - db rr 100 ripple rejection v r(rms) < 200 mv; f = 100 hz; g v =0db - 75 - db a cs channel separation 250 hz f 10 khz; g v =0db 90 96 - db type number package name description version TEA6324t so24 plastic small outline package; 24 leads; body width 7.5 mm sot137-1
1997 mar 13 3 philips semiconductors preliminary speci?cation sound control circuit TEA6324t block diagram fig.1 block diagram. handbook, full pagewidth mgk105 3.4 k w 3.4 k w 5.6 nf 10 nf mute c m 100 m f 47 m f power supply volume i left + 20 to - 31 db source selector input left source input right source input mono source bass left 18 db treble left 12 db volume i right + 20 to - 31 db bass right 18 db treble right 12 db mute function zero cross detector volume ii 0 to - 55 db balance output left i 2 c-bus receiver volume ii 0 to - 55 db balance output right logic TEA6324t c kvl v ref 220 nf 270 nf 270 nf 5.6 nf c kvl c kin 220 nf 270 nf 17 18 20 21 49 5 6 7 8 16 23 2 gnd v cc 15 12 5 220 nf 10 14 13 11 22 1 24 3 19 270 nf scl sda
1997 mar 13 4 philips semiconductors preliminary speci?cation sound control circuit TEA6324t pinning symbol pin description sda 1 serial data input/output (i 2 c-bus) gnd 2 ground outl 3 output left tl 4 treble control capacitor left channel or input from an external equalizer b2l 5 bass control left channel or output to an external equalizer b1l 6 bass control, left channel ivl 7 input volume i, left control part qsl 8 output source selector, left channel mute 9 mute control imo 10 input mono source ibl 11 input b left source ial 12 input a left source iar 13 input a right source ibr 14 input b right source cap 15 electronic ?ltering for supply v ref 16 reference voltage (0.5v cc ) qsr 17 output source selector right channel ivr 18 input volume i, right control part b1r 19 bass control right channel b2r 20 bass control right channel or output to an external equalizer tr 21 treble control capacitor right channel or input from an external equalizer outr 22 output right v cc 23 supply voltage scl 24 serial clock input (i 2 c-bus) fig.2 pin configuration. handbook, halfpage sda gnd outl tl b2l b1l ivl qsl mute imo ibl ial scl v cc outr tr b1r ivr b2r qsr v ref cap ibr iar 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 TEA6324t mgk104
1997 mar 13 5 philips semiconductors preliminary speci?cation sound control circuit TEA6324t functional description the source selector selects one of 2 stereo inputs or the mono input. the maximum input signal voltage is v i(rms) = 2 v. the outputs of the source selector and the inputs of the following volume control parts are available at pins 7 and 8 for the left channel and pins 17 and 18 for the right channel. this offers the possibility of interfacing a noise reduction system. the volume control function is split into two sections: volume i control block and volume ii control block. the control range of volume i is between +20 db and - 31 db in steps of 1 db. the volume ii control range is between 0 db and - 55 db in steps of 1 db. the recommended control range to be used is 86 db (+20 to - 66 db) although in theory, a range of 106 db (+20 to - 86 db) can be attained. the gain/attenuation setting of the volume i control block is common for both channels. the volume i control block is followed by the bass control block. the frequency response of the bass control (see fig.3) is provided for each channel by an external filter in combination with internal resistors. the adjustable range is between - 18 and +18 db in steps of 1.8 db at 46 hz. the treble control block offers a control range between - 12 and +12 db in steps of 1.5 db at 15 khz. the filter characteristic is determined by a single capacitor of 5.6 nf for each channel in combination with internal resistors (see fig.4). the basic step width of treble control is 3 db. the intermediate steps are obtained by switching 1.5 db boost and 1.5 db attenuation steps. the bass and treble control functions can be switched off via i 2 c-bus. in this event the internal signal flow is disconnected. the connections b2l and b2r are outputs and tl and tr are inputs for inserting an external equalizer. the last section of the circuit is the volume ii block. the balance function uses the same control block. this is achieved by 2 independently controllable attenuators, one for each output. the control range of these attenuators is 55 db in steps of 1 db with an additional mute step. the circuit provides 3 mute modes: 1. zero crossing mode mute via i 2 c-bus using 2 independent zero crossing detectors (zcm, see tables 2 and 8 and fig.15) 2. fast mute via mute pin (see fig.9) 3. fast mute via i 2 c-bus either by general mute (gmu, see tables 2 and 8) or volume ii block setting (see table 4). the mute function is performed immediately if zcm is cleared (zcm = 0). if the bit is set (zcm = 1) the mute is activated after changing the gmu bit. the actual mute switching is delayed until the next zero crossing of the audio frequency signal. two comparators are built-in to provide independent mute switches to control each of the audio channels (left and right). to avoid a large delay of mute switching when very low frequencies are processed, the maximum delay time is limited to typically 100 ms by an integrated timing circuit and an external capacitor (c m = 10 nf, see fig.9). this timing circuit is triggered by reception of a new data word for the switch function which includes the gmu bit. after a discharge and charge period of an external capacitor the muting switch follows the gmu bit, only if no zero crossing was detected during that time. the mute function can also be controlled externally (see fig.9). if the mute pin is switched to ground all outputs are muted immediately (hardware mute). this mute request overwrites all mute controls via the i 2 c-bus for the time the pin is held low. the hardware mute position is not stored in the TEA6324t. typically, the turn on/off can be used to avoid af output. this can be caused by the input signal from preceding stages, which may produce output during a drop of v cc . to avoid this, the mute must be set prior to a v cc drop and can be achieved either by i 2 c-bus control, or by grounding the mute pin. in cases where there is no mute in the application before turn off, a supply voltage drop of more than 1 v be will result in a mute during the voltage drop. the power supply should include a v cc buffer capacitor, which provides a discharging time constant. if the input signal does not disappear after turn off the input will become audible after a certain time. a 4.7 k w resistor discharges the v cc buffer capacitor, because the internal current of the ic does not discharge it completely. the hardware mute function is ideal for use in radio data system (rds) applications. the zero crossing mute avoids modulation plops. this feature is an advantage for mute during changing presets and/or sources (e.g. traffic announcement during cassette playback).
1997 mar 13 6 philips semiconductors preliminary speci?cation sound control circuit TEA6324t limiting values in accordance with the absolute maximum rating system (iec 134). note 1. human body model: c = 100 pf; r = 1.5 k w ; v 3 2 kv. machine model: c = 200 pf; r = 0 w ; v 3 500 v. symbol parameter conditions min. max. unit v cc supply voltage 0 10 v v n voltage at all pins relative to pin 2 0 v cc v t amb operating ambient temperature - 40 +85 c t stg storage temperature - 65 +150 c v es electrostatic handling note 1 --
1997 mar 13 7 philips semiconductors preliminary speci?cation sound control circuit TEA6324t characteristics v cc = 8.5 v; r s = 600 w ; r l =10k w ; c l = 2.5 nf; ac coupled; f = 1 khz; t amb =25 c; gain control g v = 0 db; bass linear; treble linear; balance in mid position; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit v cc supply voltage 7.5 8.5 9.5 v i cc supply current - 26 33 ma v dc internal dc voltage at inputs and outputs 3.83 4.25 4.68 v v ref internal reference voltage at pin 16 - 4.25 - v g v(max) maximum voltage gain r s =0 w ; r l = 19 20 21 db v o(rms) output voltage level (rms value) for p max at the power output stage thd 0.1%; see fig.10 - 2000 - mv start of clipping thd = 1% 2300 -- mv r l =2k w ; c l = 10 nf; thd = 1% 2000 -- mv v i(rms) input sensitivity v o = 2000 mv; g v =20db - 200 - mv f ro roll-off frequency c kin = 220 nf; c kvl = 220 nf; z i =z i(min) low frequency ( - 1 db) 60 -- hz low frequency ( - 3 db) 30 -- hz high frequency ( - 1 db) 20000 -- hz c kin = 470 nf; c kvl = 100 nf; z i =z i(typ) low frequency ( - 3 db) 17 -- hz a cs channel separation v i = 2 v; frequency range 250 hz to 10 khz 90 96 - db thd total harmonic distortion frequency range 20 hz to 12.5 khz v i = 100 mv; g v =20db - 0.1 - % v i = 1 v; g v =0db - 0.05 0.15 % v i = 2 v; g v =0db - 0.1 - % v i = 2 v; g v = - 10 db - 0.1 - % rr ripple rejection v r(rms) < 200 mv f = 100 hz 70 76 - db f = 40 hz to 12.5 khz - 66 - db (s+n)/n signal-plus-noise to noise ratio unweighted; 20 hz to 20 khz rms; v o = 2.0 v; see figs 5 and 6 - 105 - db ccir468-2 weighted; quasi peak; v o = 2.0 v g v =0db - 95 - db g v =12db - 88 - db g v =20db - 81 - db
1997 mar 13 8 philips semiconductors preliminary speci?cation sound control circuit TEA6324t p no(rms) noise output power (rms value) only contribution of TEA6324t; power ampli?er for 6 w mute position; note 1 -- 10 nw a ct crosstalk between bus inputs and signal outputs note 2 - 110 - db source selector z i input impedance 25 35 45 k w a s input isolation of one selected source to any other input f = 1 khz - 105 - db f = 12.5 khz - 95 - db v i(rms) maximum input voltage (rms value) thd < 0.5%; v cc = 8.5 v - 2.15 - v thd < 0.5%; v cc = 7.5 v - 1.8 - v v offset dc offset voltage at source selector output by selection of any inputs -- 10 mv z o output impedance - 80 120 w r l output load resistance 10 -- k w c l output load capacity 0 - 2500 pf g v voltage gain, source selector - 0 - db control part (source selector disconnected; source resistance 600 w ) z i input impedance volume input 100 150 200 k w z o output impedance - 80 120 w r l output load resistance 2 -- k w c l output load capacity 0 - 10 nf r dcl dc load resistance at output to ground 4.7 -- k w v i(rms) maximum input voltage (rms value) thd < 0.5% - 2.15 - v v n(o) noise output voltage ccir468-2 weighted; quasi peak g v =20db - 110 220 m v g v =0db - 33 50 m v g v = - 66 db - 13 22 m v mute position - 10 -m v cr tot total continuous control range - 106 - db recommended control range - 86 - db g step step resolution - 1 - db step error between any adjoining step -- 0.5 db d g a attenuator set error g v = +20 to - 50 db -- 2db g v = - 51 to - 66 db -- 3db d g t gain tracking error g v = +20 to - 50 db -- 2db a mute mute attenuation see fig.9 100 110 - db symbol parameter conditions min. typ. max. unit 20 v bus p p C () v o rms () -------------------------- - log ? ? ??
1997 mar 13 9 philips semiconductors preliminary speci?cation sound control circuit TEA6324t v offset dc step offset between any adjoining step g v =0to - 66 db - 0.2 10 mv g v =20to0db - 215mv dc step offset between any step to mute g v =0to - 66 db -- 10 mv volume i control cr tot(vol)1 continuous volume control range - 51 - db g v voltage gain - 31 - +20 db g step step resolution - 1 - db bass control g bass bass control, maximum boost f = 46 hz 16 18 19 db maximum attenuation f = 46 hz 16 18 19 db g step step resolution (toggle switching) f = 46 hz - 1.8 - db step error between any adjoining step f = 46 hz -- 0.5 db v offset dc step offset in any bass position -- 25 mv treble control g treble treble control, maximum boost f = 15 khz 11 12 13 db maximum attenuation f = 15 khz 11 12 13 db maximum boost f > 15 khz -- 15 db g step step resolution (toggle switching) f = 15 khz - 1.5 - db step error between any adjoining step f = 15 khz -- 0.5 db v offset dc step offset in any treble position -- 10 mv volume ii and balance control cr tot(vol)2 continuous attenuation of volume control range 53.5 55 56.5 db g step step resolution - 12db attenuation set error -- 1.5 db mute function (see fig.9) h ardware mute v sw mute switch level (2 v be ) - 1.45 - v mute active v swlow input level -- 1.0 v i i input current v swlow =1v - 300 --m a mute passive: level internally de?ned v swhigh saturation voltage -- v cc v t d(mute) delay until mute passive -- 0.5 ms z ero crossing mute i dch discharge current 0.3 0.6 1.2 m a i ch charge current - 300 - 150 -m a v swdel delay switch level (3 v be ) - 2.2 - v symbol parameter conditions min. typ. max. unit
1997 mar 13 10 philips semiconductors preliminary speci?cation sound control circuit TEA6324t notes to the characteristics 1. the indicated values for output power assume a 6 w power amplifier at 4 w with 20 db gain and a fixed attenuator of 12 db in front of it. signal-to-noise ratios exclude noise contribution of the power amplifier. 2. the transmission contains: total initialization with mad and subaddress for volume and 8 data words, see also definition of characteristics, clock frequency = 50 khz, repetition burst rate = 400 hz, maximum bus signal amplitude = 5 v (p-p). 3. the ac characteristics are in accordance with the i 2 c-bus specification. this specification, the i 2 c-bus and how to use it , can be ordered using the code 9398 393 40011. t d delay time c m =10nf - 100 - ms v (w) window for audio signal zero crossing detection - 30 40 mv muting at power supply drop v ccdrop supply drop for mute active - v 23 - 0.7 - v power-on reset when reset is active the gmu-bit (general mute) is set and the i 2 c-bus receiver is in reset position v cc increasing supply voltage start of reset -- 2.5 v end of reset 5.2 6.5 7.2 v decreasing supply voltage start of reset 4.2 5.5 6.2 v digital part (i 2 c-bus pins); note 3 v ih high-level input voltage 3 - 9.5 v v il low-level input voltage - 0.3 - +1.5 v i ih high-level input current - 10 - +10 m a i il low-level input current - 10 - +10 m a v ol low-level output voltage i l =3ma -- 0.4 v symbol parameter conditions min. typ. max. unit
1997 mar 13 11 philips semiconductors preliminary speci?cation sound control circuit TEA6324t i 2 c-bus protocol i 2 c-bus format notes 1. s = start condition. 2. slave address (mad) = 0101 0000. 3. a = acknowledge, generated by the slave. 4. subaddress (sad), see table 1. 5. data, see table 1. 6. p = stop condition. table 1 second byte after mad note 1. significant subaddress. s (1) slave address (2) a (3) subaddress (4) a (3) data (5) a (3) p (6) function bit msb lsb 765432 (1) 1 (1) 0 (1) volume v 00000000 output right outr 00000001 output left outl 00000010 no function - 00000011 no function - 00000100 bass ba 00000101 treble tr 00000110 switch s 00000111
1997 mar 13 12 philips semiconductors preliminary speci?cation sound control circuit TEA6324t table 2 de?nition of third byte after mad and sad notes 1. zero crossing mode. 2. volume control. 3. dont care bits (logic 1 during testing). 4. output right. 5. output left. 6. bass control. 7. treble control. 8. mute control for all outputs (general mute). 9. source selector control. function bit msb lsb 76543210 volume v zcm (1) 1v5 (2) v4 (2) v3 (2) v2 (2) v1 (2) v0 (2) output right outr x (3) x (3) outr5 (4) outr4 (4) outr3 (4) outr2 (4) outr1 (4) outr0 (4) output left outl x (3) x (3) outl5 (5) outl4 (5) outl3 (5) outl2 (5) outl1 (5) outl0 (5) no function - x (3) x (3) x (3) x (3) x (3) x (3) x (3) x (3) no function - x (3) x (3) x (3) x (3) x (3) x (3) x (3) x (3) bass ba x (3) x (3) x (3) ba4 (6) ba3 (6) ba2 (6) ba1 (6) ba0 (6) treble tr x (3) x (3) x (3) tr4 (7) tr3 (7) tr2 (7) tr1 (7) tr0 (7) switch s gmu (8) x (3) x (3) x (3) x (3) sc2 (9) sc1 (9) sc0 (9)
1997 mar 13 13 philips semiconductors preliminary speci?cation sound control circuit TEA6324t table 3 volume i setting g v (db) data v5 v4 v3 v2 v1 v0 +20 1 1 1 1 1 1 +19 1 1 1 1 1 0 +18 1 1 1 1 0 1 +17 1 1 1 1 0 0 +16 1 1 1 0 1 1 +15 1 1 1 0 1 0 +14 1 1 1 0 0 1 +13 1 1 1 0 0 0 +12 1 1 0 1 1 1 +11 110110 +10 1 1 0 1 0 1 +9 110100 +8 110011 +7 110010 +6 110001 +5 110000 +4 101111 +3 101110 +2 101101 +1 101100 0 101011 - 1 101010 - 2 101001 - 3 101000 - 4 100111 - 5 100110 - 6 100101 - 7 100100 - 8 100011 - 9 100010 - 10 100001 - 11 100000 - 12 011111 - 13 011110 - 14 011101 - 15 011100 - 16 011011 - 17 011010
1997 mar 13 14 philips semiconductors preliminary speci?cation sound control circuit TEA6324t - 18 011001 - 19 011000 - 20 010111 - 21 010110 - 22 010101 - 23 010100 - 24 010011 - 25 010010 - 26 010001 - 27 010000 - 28 001111 - 29 001110 - 30 001101 - 31 001100 repetition of steps in a range from - 28 db to - 31 db - 28 001011 - 29 001010 - 30 001001 - 31 001000 - 28 000111 - 29 000110 - 30 000101 - 31 000100 - 28 000011 - 29 000010 - 30 000001 - 31 000000 g v (db) data v5 v4 v3 v2 v1 v0
1997 mar 13 15 philips semiconductors preliminary speci?cation sound control circuit TEA6324t table 4 volume ii setting; note 1 g v (db) data outl5 outl4 outl3 outl2 outl1 outl0 outr5 outr4 outr3 outr2 outr1 outr0 0 111111 - 1 111110 - 2 111101 - 3 111100 - 4 111011 - 5 111010 - 6 111001 - 7 111000 - 8 110111 - 9 110110 - 10 110101 - 11 110100 - 12 110011 - 13 110010 - 14 110001 - 15 110000 - 16 101111 - 17 101110 - 18 101101 - 19 101100 - 20 101011 - 21 101010 - 22 101001 - 23 101000 - 24 100111 - 25 100110 - 26 100101 - 27 100100 - 28 100011 - 29 100010 - 30 100001 - 31 100000 - 32 011111 - 33 011110 - 34 011101 - 35 011100 - 36 011011
1997 mar 13 16 philips semiconductors preliminary speci?cation sound control circuit TEA6324t note 1. for a particular range the data is always the same, only the subaddress changes. - 37 011010 - 38 011001 - 39 011000 - 40 010111 - 41 010110 - 42 010101 - 43 010100 - 44 010011 - 45 010010 - 46 010001 - 47 010000 - 48 001111 - 49 001110 - 50 001101 - 51 001100 - 52 001011 - 53 001010 - 54 001001 - 55 001000 mute 0 0 0 1 1 1 mute 0 0 0 1 1 0 mute 0 0 0 1 0 1 mute 0 0 0 1 0 0 mute 0 0 0 0 1 1 mute 0 0 0 0 1 0 mute 0 0 0 0 0 1 mute 0 0 0 0 0 0 g v (db) data outl5 outl4 outl3 outl2 outl1 outl0 outr5 outr4 outr3 outr2 outr1 outr0
1997 mar 13 17 philips semiconductors preliminary speci?cation sound control circuit TEA6324t table 5 bass setting notes 1. recommended data word for step 0 db. 2. result of 1.8 db boost and 1.8 db attenuation. 3. the last four bass control data words mute the bass response. 4. the last bass control and treble control data words (00000) enable the external equalizer connection. g bass (db) data ba4 ba3 ba2 ba1 ba0 +18.0 11111 +16.2 11110 +18.0 11101 +16.2 11100 +18.0 11011 +16.2 11010 +14.4 11001 +12.6 11000 +10.8 10111 +9.0 10110 +7.2 10101 +5.4 10100 +3.6 10011 +1.8 10010 0 (1) 10001 0 (2) 10000 - 1.8 01111 - 3.6 01110 - 5.4 01101 - 7.2 01100 - 9.0 01011 - 10.8 01010 - 12.6 01001 - 14.4 01000 - 16.2 00111 - 18.0 00110 - 16.2 00101 - 18.0 00100 note 3 00011 note 3 00010 note 3 00001 notes 3 and 4 00000
1997 mar 13 18 philips semiconductors preliminary speci?cation sound control circuit TEA6324t table 6 treble setting notes 1. recommended data word for step 0 db. 2. result of 1.5 db boost and 1.5 db attenuation. 3. the last eight treble control data words select treble output. 4. the last treble control and bass control data words (00000) enable the external equalizer connection. g treble (db) data tr4 tr3 tr2 tr1 tr0 +12.0 11111 +10.5 11110 +12.0 11101 +10.5 11100 +12.0 11011 +10.5 11010 +12.0 11001 +10.5 11000 +9.0 10111 +7.5 10110 +6.0 10101 +4.5 10100 +3.0 10011 +1.5 10010 0 (1) 10001 0 (2) 10000 - 1.5 01111 - 3.0 01110 - 4.5 01101 - 6.0 01100 - 7.5 01011 - 9.0 01010 - 10.5 01001 - 12.0 01000 note 3 00111 note 3 00110 note 3 00101 note 3 00100 note 3 00011 note 3 00010 note 3 00001 notes 3 and 4 00000
1997 mar 13 19 philips semiconductors preliminary speci?cation sound control circuit TEA6324t table 7 selected input note 1. x = dont care bits (logic 1 during testing). function data sc2 sc1 sc0 stereo inputs ial and iar 1 1 1 stereo inputs ibl and ibr 1 1 0 no function 1 0 1 no function 1 0 0 mono input imo 0 x (1) x (1) table 8 mute mode function data gmu zcm direct mute off 0 0 mute off delayed until the next zero crossing 01 direct mute 1 0 mute delayed until the next zero crossing 11
1997 mar 13 20 philips semiconductors preliminary speci?cation sound control circuit TEA6324t fig.3 bass control. handbook, full pagewidth - 20 - 10 20 10 4 10 3 10 2 10 10 0 f (hz) g bass (db) med840 fig.4 treble control. handbook, full pagewidth - 15 - 10 - 5 15 10 5 10 4 10 3 2 10 5 10 0 f (hz) g treble (db) med424
1997 mar 13 21 philips semiconductors preliminary speci?cation sound control circuit TEA6324t fig.5 signal-to-noise ratio; noise weighted: ccir468-2, quasi peak. handbook, full pagewidth 50 100 1 10 10 - 1 10 - 2 10 - 3 10 - 4 med426 60 70 80 90 p o (w) s/n (db) (1) (2) (3) (1) v i = 2.0 v. (2) v i = 0.5 v. (3) v i = 0.2 v. fig.6 signal-to-noise ratio; v i = 2 v; p max =6w. handbook, full pagewidth 60 110 1 10 10 - 1 10 - 2 10 - 3 10 - 4 med427 70 80 90 100 p o (w) s/n (db) (1) (2) (3) (1) unweighted rms. (2) ccir468-2 rms. (3) ccir468-2 quasi peak.
1997 mar 13 22 philips semiconductors preliminary speci?cation sound control circuit TEA6324t fig.7 noise output voltage; ccir468-2, quasi peak. stereo/mono inputs. handbook, full pagewidth 30 200 150 50 0 - 70 - 50 - 30 - 10 10 mha594 100 gain (db) noise ( m v) fig.8 muting. handbook, full pagewidth - 60 - 80 - 100 - 120 - 140 med429 f (hz) (db) 10 2 10 3 2 x 10 3 5 x 10 3 10 4 2 x 10 4 50 20 500 200
1997 mar 13 23 philips semiconductors preliminary speci?cation sound control circuit TEA6324t fig.9 mute function diagram. (1) typically 2.2 v; referenced to 3 v be . (2) typically 1.5 v; referenced to 2 v be . handbook, full pagewidth mha595 TEA6324t i ch = - 150 m a i dch = 0.6 m a c m = 10 nf hardware mute switch mute (pin 9) 2.2 1.45 0 - 150 t d(mute) = 0.5 ms delay until mute passive 100 ms t (ms) u (v) v cc 8.5 delay switch (1) level mute switch (2) level i ( m a) zero crossing mute start end of delay hard mute on hard mute off
1997 mar 13 24 philips semiconductors preliminary speci?cation sound control circuit TEA6324t in cases where at the maximum volume position the 20 db gain is not needed, it is recommended that the maximum boost gain should be used. this coupled with increased attenuation in the last section (volume ii), results in a lower noise and offset voltage. fig.10 level diagram. a. gain volume i = 20 db (g v(max) ); gain volume ii = 0 db; control range = 55 db. b. gain volume i = 20 db (g v(max) ); gain volume ii = - 6 db global setting; control range now 49 db, previously 55 db. a. b. handbook, halfpage v o = 2 v for p (max) power stage g = 20 db TEA6324t p (max) = 100 w at 4 w v i(min) = 200 mv mha596 handbook, halfpage v o = 1 v for p (max) power stage g = 26 db TEA6324t p (max) = 100 w at 4 w v i(min) = 200 mv mha597
1997 mar 13 25 philips semiconductors preliminary speci?cation sound control circuit TEA6324t fig.11 turn-on/off power supply circuit diagram. handbook, full pagewidth 5 220 nf 2 4.7 m f 5 600 w 4.7 k w 2 10 k w inputs 13 11 TEA6324t 14 10 12 21516 22 23 v cc 8.5 v v p 3 outputs to oscilloscope + 8.5 v to oscilloscope 47 m f 470 m f 100 m f mha598 fig.12 turn-on/off behaviour. handbook, full pagewidth 5 10 0 01234 med433 2 4 6 8 t (s) (v) (1) (2) (1) v cc . (2) v o .
1997 mar 13 26 philips semiconductors preliminary speci?cation sound control circuit TEA6324t fig.13 test circuit for power supply ripple rejection (rr). handbook, full pagewidth 10 nf 5.6 nf 5.6 nf 270 nf 8 16 23 2 v cc = 8.5 v 76 5 TEA6324t 49 scl sda 3.4 k w 600 w 10 k w 270 nf 270 nf 3.4 k w 270 nf 220 nf 220 nf 220 nf 100 m f 0.1 m f 15 v p v o 0.2 v (rms) 17 18 19 20 21 mha599 1 24 47 m f 4.7 m f 1000 m f input a and b left and right and input mono output right output left fig.14 test circuit for channel separation ( a cs ). handbook, full pagewidth 10 nf 5.6 nf 5.6 nf 270 nf 8 16 23 2 v cc = 8.5 v 76 5 TEA6324t 49 scl sda 3.4 k w 600 w 270 nf 270 nf 3.4 k w 270 nf 220 nf 220 nf 220 nf 220 nf 100 m f 0.1 m f 470 m f 15 input a and b right and left v p v i v o 17 18 19 20 21 mha600 1 24 47 m f 4.7 m f input a and b left and right and input mono output right output left
1997 mar 13 27 philips semiconductors preliminary speci?cation sound control circuit TEA6324t selection of input signals by using the zero crossing mute mode the zero cross mute mode provides for a selection of input sources (a and b) for both left and right channels. the following example (see fig.15), shows a typical selection for the left input source signals ial and ibl. the initial selection of these channels produces a modulation click. the click is determined by the difference of the signal values at the time of switching. at t 1 the maximum possible difference between signals is 7 v (p-p) (see fig.15) and gives a large click. using the cross detector no modulation click is audible. with the selection enabled at t 1 , the microcontroller sets the zero cross bit (zcm = 1) and then the mute bit (gmu = 1) via the i 2 c-bus. the output signal follows the input a signal from - 4 v, until the next zero crossing occurs and then activates mute. after a fixed delay time at t 2 , the microcontroller sends the bits for input switching and mute inactive. the output signal remains muted until the next signal zero crossing of input b (ibl) occurs, and then follows that signal up to 3 v. with a delay time of 40 ms (t 2 - t 1 ), the external capacitor c m = 3.3 nf. this results with the zero cross function operating at the lowest frequency of 40 hz determined by the c m capacitor. fig.15 zero cross function; only one channel shown. handbook, full pagewidth v t t 1 4 0 - 1 - 2 - 3 - 4 1 2 3 t 2 med436 (1) (2) (3) (1) input a (ial). (2) output. (3) input b (ibl).
1997 mar 13 28 philips semiconductors preliminary speci?cation sound control circuit TEA6324t internal pin configurations values shown in figs 16 to 27 are typical dc values; v cc = 8.5 v. fig.16 pin 1: sda (i 2 c-bus data). 5 v 1.8 k w mbe911 1 fig.17 pins 3 and 22: output signals. 4.25 v 80 w + mbe912 3 fig.18 pins 4 and 21: treble control capacitors. 4 4.25 v mha601 + 2.4 k w fig.19 pins 5 and 20: bass control capacitor outputs. 5 4.25 v 80 w mha602 +
1997 mar 13 29 philips semiconductors preliminary speci?cation sound control circuit TEA6324t fig.20 pins 6 and 19: bass control capacitor inputs. 6 4.25 v mha603 + 3.52 k w fig.21 pins 7 and 18: input volume 1, control part. 7 4.25 v 4.25 v 150 k w mha604 + fig.22 pins 8 and 17: output source selector. 8 4.25 v 80 w mha605 + fig.23 pin 9: mute control. 9 8.5 v 1.3 k w 4.5 k w 0.6 m a constant maximum 200 m a mha606 + constant 2.2 v
1997 mar 13 30 philips semiconductors preliminary speci?cation sound control circuit TEA6324t fig.24 pins 10 to 14: inputs. 10 4.25 v 4.25 v 35 k w mha607 + fig.25 pin 15: filtering for supply; pin 16: reference voltage. 8.5 v 4.25 v 5 k w 4.7 k w 300 w 3.4 k w 3.4 k w mha608 + + 15 16 fig.26 pin 23: supply voltage. 23 apply + 8.5 v to this pin mha609 fig.27 pin 24: scl (i 2 c-bus clock). 24 mha610 5 v 1.8 k w
1997 mar 13 31 philips semiconductors preliminary speci?cation sound control circuit TEA6324t package outline unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec eiaj mm inches 2.65 0.30 0.10 2.45 2.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.1 0.4 sot137-1 x 12 24 w m q a a 1 a 2 b p d h e l p q detail x e z c l v m a 13 (a ) 3 a y 0.25 075e05 ms-013ad pin 1 index 0.10 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.61 0.60 0.30 0.29 0.050 1.4 0.055 0.42 0.39 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 92-11-17 95-01-24 e 1 0 5 10 mm scale so24: plastic small outline package; 24 leads; body width 7.5 mm sot137-1
1997 mar 13 32 philips semiconductors preliminary speci?cation sound control circuit TEA6324t soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all so packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering techniques can be used for all so packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1997 mar 13 33 philips semiconductors preliminary speci?cation sound control circuit TEA6324t definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1997 mar 13 34 philips semiconductors preliminary speci?cation sound control circuit TEA6324t notes
1997 mar 13 35 philips semiconductors preliminary speci?cation sound control circuit TEA6324t notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1997 sca53 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - 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